Multi-Modulus Dividers (MMDs) are key circuit building blocks in PLL-based frequency generation for RF transceivers. Basically, a MMD divides the frequency of its input signal by a programmable divider value. Consider an exemplary transceiver PLL incorporating three MMDs: feedback MMD, LO (Local Oscillator) MMD for receive, and TX MMD for transmit.
As MMDs have to cope with multi-GHz signals, problems arise when the maximum speed of the MMD is not sufficient or the power consumption is too high. Furthermore, the duty cycle of the MMD output signal can be important. While this is not the case for the feedback divider, the TX MMD has to deliver 50% duty cycle output. Otherwise the linearity of the output stage suffers and harmonics occur in the transmit spectrum.